I2C (also referred to as I2C) is a multi-master serial single-ended bus used for attaching low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic devices. The I2C bus includes a clock (SCL) and data (SDA) lines with 7-bit addressing. The bus has two roles for devices: master and slave. A master device is a node that generates the clock and initiates communication with slave devices. A slave device is a node that receives the clock and responds when addressed by the master device. The I2C bus is a multi-master bus which means any number of master devices can be present. Additionally, master and slave roles may be changed between messages (after a STOP is sent). I2C defines basic types of messages, each of which begins with a START and ends with a STOP.
In this context of a camera implementation, unidirectional transmissions may be used to capture an image from a sensor and transmit such image data to memory in a baseband processor, while control data may be exchanged between the baseband processor and the sensor as well as other peripheral devices. In one example, a Camera Control Interface (CCI) protocol may be used for such control data between the baseband processor and the image sensor (and/or one or more slave devices). In one example, the CCI protocol may be implemented over an I2C serial bus between the image sensor and the baseband processor.
An extension to CCI called CCIe (Camera Control Interface extended) has been developed that encodes information for transmission over the shared bus. CCIe does not implement a separate clock line on the shared bus. Instead, it embeds a clock within the transmitted transcoded information. However, such embedded clock may serve for reception of data and/or synchronization purposes, it may be insufficient to permit saving such data into registers.
Additionally, a mechanism is needed to allow slave devices to go into a power saving or sleep mode but also allow a master device to write data to the slave device. This may be done by having the master device track slave devices that are in sleep mode, but such mechanism adds unwanted overhead.
Therefore, a solution is needed that efficiently uses a recovered clock embedded within a transmission to allow writing data into registers of a slave device without a free-running clock while facilitating an efficient sleep and wakeup mechanism for slave devices.